Skip to main content
Scour
Browse
Getting Started
Login
Sign Up
You are offline. Trying to reconnect...
Close
Copied to clipboard
Close
Unable to share or copy to clipboard
Close
🔌 FPGA Programming
HDL, Verilog, VHDL, Hardware Synthesis, Reconfigurable Computing
Filter Results
Timeframe
Fresh
Past Hour
Today
This Week
This Month
Feeds to Scour
Subscribed
All
Scoured
121890
posts in
35.1
ms
Verilean/sparkle
: A type-safe, formally verifiable
HDL
compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.
🔧
Embedded Rust
github.com
·
3d
·
Hacker News
·
…
RTLSeek
: Boosting the LLM-Based RTL Generation with Multi-Stage
Diversity-Oriented
Reinforcement Learning
💬
Prompt Engineering
arxiv.org
·
2d
·
…
Super
Hi
International Holding Ltd. (
HDL
) Q4 2025 Earnings Call Transcript
⚡
Intel TSX
seekingalpha.com
·
1d
·
…
Automated
Multiphysics
For Successful
3D-IC
Design
⚙️
CPU Microarchitecture
semiengineering.com
·
15h
·
…
The
Synthesis
Problem: Why I’m Building a New Logic
Toolchain
🎭
Program Synthesis
llama.gs
·
6d
·
Hacker News
·
…
New comment by
renoir42
in "Ask HN: Who wants to be
hired
? (April 2026)"
✨
Gleam
github.com
·
10h
·
Hacker News
·
…
Microcontrollers
🎛️
Microcontrollers
ti.com
·
5d
·
…
FPGAs
in Space
🔌
Embedded Systems
embedded.com
·
3d
·
…
Bad Benchmarks and a Fourier-Analytic Framework for Characterizing the (Un)
Hideability
of
Combinational-Logic
Circuits
🌐
Zero-Suppressed BDDs
eprint.iacr.org
·
3d
·
…
Generalizable
Verilog
Modeling Framework for
Synchronous
and Asynchronous Superconducting Pulse-Based Logic Gates
⚛️
Quantum Computing
arxiv.org
·
3d
·
…
Formally
verifying
digital circuits with category theory in Lean
∘
Category Theory
matt.hunzinger.me
·
5d
·
r/programming
·
…
Introduction
to
Embedded
Systems
🔌
Embedded Systems
amazon.com
·
6d
·
r/embedded
·
…
Physical Design of
UET-RVMCU
: A Streamlined Open-Source RISC-V Microcontroller
⚡
RISC-V
arxiv.org
·
2d
·
…
Designing
FSMs
Specifications
from Requirements with GPT 4.0
🧪
Jepsen Testing
arxiv.org
·
1d
·
…
Efficient Conflict-Free
NTT
Hardware Architecture with Single-Port RAMs: Applications to
ML-DSA
🎛️
SmartNICs
eprint.iacr.org
·
3d
·
…
In-Depth Analysis of 187 Publications on Hardware Reverse Engineering (
Ruhr
U.,
MPI
)
🔍
Reverse Engineering
semiengineering.com
·
6d
·
…
AXON: An Automated
Netlist
Optimization Framework for High-Speed
Adders
🚀
Superoptimization
arxiv.org
·
2d
·
…
VolTune
: A Fine-Grained Runtime
Voltage
Control Architecture for FPGA Systems
🔧
Embedded Rust
arxiv.org
·
3d
·
…
FireBridge
: Cycle-Accurate Hardware + Firmware Co-Verification for Modern
Accelerators
⚡
Hardware Acceleration
arxiv.org
·
3d
·
…
AutoPDR
: Circuit-Aware
Solver
Configuration Prediction for Hardware Model Checking
🎲
Hardware Branch Prediction
arxiv.org
·
6d
·
…
Loading...
Loading more...
Page 2 »
Keyboard Shortcuts
Navigation
Next / previous item
j
/
k
Open post
o
or
Enter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
g
h
Interests
g
i
Feeds
g
f
Likes
g
l
History
g
y
Changelog
g
c
Settings
g
s
Browse
g
b
Search
/
Pagination
Next page
n
Previous page
p
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc
Press
?
anytime to show this help